Low Power Self-timed Size Optimization for an Input Data Distribution

Power conservation has become an increasingly important issue among modern digital circuit designers. As the digital technology evolution takes us into the 21st century coupled with ground breaking system performance, the power consumed by these circuits are at record highs. In fact, power dissipation or energy loss in the form of heat is reaching levels comparable to nuclear reactors. The negative affect associated with the power dissipation compromises or in many cases, impair chip reliability and life expectancy. Over the past decade, research in this area has eased but not solved this power issue. Many solutions involved increasing chip parameter size to ease the chips density that has lead us to this hot spot. However, as the demand for portable electronic devices rise, scaling technology forces us to deal with this problem. Remarkably enough, if research does not produced a technique to break through the “power wall”, advancements in circuit technology will have reached its limits.